The invention relates to semiconductor devices and more particularly to devices comprising bi-material assemblies adhesively bonded at the ends.
Thermal stresses contribute significantly to the finite service life of microelectronic and photonic components and devices. These stresses can lead to mechanical (structural), and functional (electrical or optical) failure. Therefore, the ability to predict and possibly minimize the thermal stresses and displacements in a microelectronic or photonic assembly is important.
In particular, large chips (for example 2xe2x80x3xc3x972xe2x80x3) are typically adhesively bonded to a substrates such as ceramic to provide mechanical strength and protect solder joints. Traditionally the entire chip under-surface is coated with adhesive. For large chips it may be difficult to cover the entire surface. Reduction in coverage may lead to a decrease in mechanical stability of the bonded area, particularly when the assembly is subjected to temperature changes. Accordingly, a method is needed to determine the ideal bonding area without jeopardizing mechanical strength.
Modeling thermal stress in structures, comprised of dissimilar materials has been performed using structural analysis and theory-of-elasticity methods. Both approaches have been employed to model the mechanical behavior of bonded joints, including microelectronics and photonics packaging. The specific needs described above have not been addressed by these methods.
A bi-material assembly comprising two adherends, adhesively bonded is disclosed. The assembly is adhesively bonded in an area consisting of a length of 2l at each and of the bonded assembly. The interface of the adherends is not completely bonded so that 2l is less than half of the assembly length. Each bonded area has an inner edge. The inner edge local interfacial shearing stress is substantially equal in magnitude to the inner edge global interfacial shearing stress causing the strength of the bi-material bonded assembly to be substantially the same as a like structure wherein 2l substantially equals half the assembly length.
Further disclosed are a method of fabricating a bi-material assembly, and a semiconductor device and fabrication method.